The present invention relates generally to fabrication of semiconductor devices, and more specifically to methods of fabricating transistor gates used in semiconductor devices.
The current practice to form small transistor gates uses increasingly smaller wavelengths of light in the lithography step(s). The current practice places increasingly stringent requirements on lithography.
U.S. Pat. No. 4,784,718 to Mitani et al. describes a method for fabricating a semiconductor device with its gate electrode and source/drain extraction electrodes being made of the same material on a GaAs substrate and with its source/drain heavily doped regions self-aligned with both gate electrode and source/drain extraction electrodes.
U.S. Pat. No. 5,202,272 to Hsieh et al. describes a method of forming a field effect-transistor formed with a deep-submicron gate.
U.S. Pat. No. 4,931,137 to Sibuet describes a process for fabricating conductor elements on a substrate mutually spaced by a submicron dimension.
U.S. Pat. No. 4,729,966 to Koshino et al. describes a process for fabricating a Schottky FET device using metal sidewalls as gates.
U.S. Pat. No. 4,648,937 to Ogura et al. describes a method of preventing asymmetric etching of lines in sub-micrometer range sidewall images transfer.
U.S. Pat. No. 6,171,937 to Lustig describes a process for fabricating an MOS transistor having a channel length of less than 100 nm.
U.S. Pat. No. 5,336,630 to Yun et al. describes a method of making a semiconductor memory device having a storage node with a plurality of pillars capable of increasing the storage node surface and thus the cell capacitance.
Accordingly, it is an object of the present invention to provide an improved method of fabricating small transistor gates.
Another object of the present invention to provide an improved method of fabricating small transistor gates that relies less on lithography than conventional methods.
It has now been discovered that the above and other objects of the present invention may be accomplished in the following manner. Specifically, a substrate is provided having an overlying Si3N4 or an SiO2/Si3N4 stack gate dielectric layer. A gate material layer is formed over the gate dielectric layer. A hard mask layer is formed over the gate material layer. The hard mask layer and the gate material layer are patterned to form a hard mask/gate material layer stack. A planarized dielectric layer is formed surrounding the hard mask/gate material layer stack. The patterned hard mask layer is removed from over the patterned gate material layer to form a cavity having exposed dielectric layer side walls. Masking spacers are formed on the exposed dielectric layer side walls over a portion of the patterned gate material layer. The patterned gate material layer is etched using the masking spacers as masks to expose a portion of the gate dielectric layer. The planarized dielectric layer is removed. The masking spacers are removed to form narrow gates comprising gate material.